512k x 8 static ram cy7c1049v33 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 june 2, 1999 3 features ? high speed ?t aa = 15 ns low active power ? 504 mw (max.) low cmos standby power (commercial l version) ? 1.8 mw (max.) 2.0v data retention (660 w at 2.0v retention) automatic power-down when deselected ttl-compatible inputs and outputs easy memory expansion with ce and oe features functional description the cy7c1049v33 is a high-performance cmos static ram organized as 524,288 words by 8 bits. easy memory expan- sion is provided by an active low chip enable (ce ), an active low output enable (oe ), and three-state drivers. writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 18 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing write enable (we ) high. under these conditions, the contents of the memory location specified by the address pins will appear on the i/o pins. the eight input/output pins (i/o 0 through i/o 7 ) are placed in a high-impedance state when the device is deselected (ce high), the outputs are disabled (oe high), or during a write operation (ce low, and we low). the cy7c1049v33 is available in a standard 400-mil-wide 36-pin soj package with center power and ground (revolution- ary) pinout. 14 15 logic block diagram pin configuration a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffer power down we oe i/o 0 i/o 1 i/o 2 i/o 3 512k x 8 array i/o 7 i/o 6 i/o 5 i/o 4 a 0 a 11 a 13 a 12 a ce a a 16 a 17 1 2 3 4 5 6 7 8 9 10 11 14 23 24 28 27 26 25 29 32 31 30 top view soj 12 13 33 36 35 34 16 15 21 22 gnd a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 we v cc a 18 a 15 a 12 a 14 i/o 5 i/o 4 1049v33?1 a 9 a 0 i/o 0 i/o 1 i/o 2 oe a 17 a 16 a 13 ce 1049v33?2 a 9 a 18 18 17 19 20 gnd i/o 7 i/o3 i/o 6 v cc a 10 a 11 nc nc a 10 selection guide 1049v33-12 1049v33-15 1049v33-17 1049v33-20 1049v33-25 maximum access time (ns) 12 15 17 20 25 maximum operating current (ma) 150 140 130 120 110 maximum cmos standby current (ma) com?l/ind?l 888 8 8 com?l l 0.5 0.5 0.5 0.5 0.5 shaded areas contain preliminary information.
cy7c1049v33 2 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 65 c to +150 c ambient temperature with power applied ............................................. ? 55 c to +125 c supply voltage on v cc to relative gnd [1] .... ? 0.5v to +4.6v dc voltage applied to outputs in high z state [1] .................................... ? 0.5v to v cc + 0.5v dc input voltage [1] ................................ ? 0.5v to v cc + 0.5v current into outputs (low)......................................... 20 ma operating range range ambient temperature [2] v cc commercial 0 c to +70 c 3.3v 0.3v industrial ? 40 c to +85 c electrical characteristics over the operating range parameter description test conditions 7c1049v33-12 7c1049v33-15 7c1049v33-17 min. max. min. max. min. max. unit v oh output high voltage v cc = min., i oh = ? 4.0 ma 2.4 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 0.4 v v ih input high voltage 2.2 v cc + 0.5 2.2 v cc + 0.5 2.2 v cc + 0.5 v v il input low voltage [1] ? 0.5 0.8 ? 0.5 0.8 ? 0.5 0.8 v i ix input load current gnd < v i < v cc ? 1 +1 ? 1+1 ? 1+1 a i oz output leakage current gnd < v out < v cc , output disabled ? 1 +1 ? 1+1 ? 1+1 a i cc v cc operating supply current v cc = max., f = f max = 1/t rc 150 140 130 ma i sb1 automatic ce power-down current ? ttl inputs max. v cc , ce > v ih v in > v ih or v in < v il , f = f max 30 30 30 ma i sb2 automatic ce power-down current ? cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f=0 com ? l/ind ? l 888ma com ? ll 0.5 0.5 0.5 ma shaded areas contain preliminary information. notes: 1. v il (min.) = ? 2.0v for pulse durations of less than 20 ns. 2. t a is the ? instant on ? case temperature.
cy7c1049v33 3 electrical characteristics over the operating range (continued) 7c1049v33-20 7c1049v33-25 parameter description test conditions min. max. min. max. unit v oh output high voltage v cc = min., i oh = ? 4.0 ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 v v ih input high voltage 2.2 v cc + 0.5 2.2 v cc + 0.5 v v il input low voltage [1] ? 0.5 0.8 ? 0.5 0.8 v i ix input load current gnd < v i < v cc ? 1+1 ? 1+1 a i oz output leakage current gnd < v out < v cc , output disabled ? 1+1 ? 1+1 a i cc v cc operating supply current v cc = max., f = f max = 1/t rc 120 110 ma i sb1 automatic ce power-down current ? ttl inputs max. v cc , ce > v ih v in > v ih or v in < v il , f = f max 30 30 ma i sb2 automatic ce power-down current ? cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f=0 com ? l/ind ? l8 8ma com ? ll 0.5 0.5 ma capacitance [3] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 8pf c out i/o capacitance 8 pf note: 3. tested initially and after any design or process changes that may affect these parameters. ac test loads and waveforms 1049v33 ? 3 1049v33 ? 4 90% 10% 3.3v gnd 90% 10% all input pulses 3.3v output 30 pf including jig and scope output (a) (b) 3 ns 3ns r1 317 ? 167 ? r2 351 ? venin equivalent th 1.73v
cy7c1049v33 4 switching characteristics [5] over the operating range 7c1049v33-12 7c1049v33-15 7c1049v33-17 parameter description min. max. min. max. min. max. unit read cycle t rc read cycle time 12 15 17 ns t aa address to data valid 12 15 17 ns t oha data hold from address change 3 33ns t ace ce low to data valid 12 15 17 ns t doe oe low to data valid 678ns t lzoe oe low to low z 0 00ns t hzoe oe high to high z [5, 6] 678ns t lzce ce low to low z [6] 3 33ns t hzce ce high to high z [5, 6] 678ns t pu ce low to power-up 0 00ns t pd ce high to power-down 12 15 17 ns write cycle [7, 8] t wc write cycle time 12 15 17 ns t sce ce low to write end 10 12 13 ns t aw address set-up to write end 10 12 13 ns t ha address hold from write end 0 00ns t sa address set-up to write start 0 00ns t pwe we pulse width 10 12 13 ns t sd data set-up to write end 7 89ns t hd data hold from write end 0 00ns t lzwe we high to low z [6] 3 33ns t hzwe we low to high z [5, 6] 678ns shaded areas contain preliminary information. notes: 4. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 5. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured 500 mv from steady-state voltage. 6. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 7. the internal write time of the memory is defined by the overlap of ce low, and we low. ce and we must be low to initiate a write, and the transition of either of these signals can terminate the write. the input data set-up and hold timing should be referenced to the leading edge of the signal t hat terminates the write. 8. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd .
cy7c1049v33 5 switching characteristics [5] over the operating range (continued) parameter description 7c1049v33-20 7c1049v33-25 unit min. max. min. max. read cycle t rc read cycle time 20 25 ns t aa address to data valid 20 25 ns t oha data hold from address change 3 5 ns t ace ce low to data valid 20 25 ns t doe oe low to data valid 8 10 ns t lzoe oe low to low z 0 0 ns t hzoe oe high to high z [5, 6] 810ns t lzce ce low to low z [6] 35ns t hzce ce high to high z [5, 6] 810ns t pu ce low to power-up 0 0 ns t pd ce high to power-down 20 25 ns write cycle [7] t wc write cycle time 20 25 ns t sce ce low to write end 13 15 ns t aw address set-up to write end 13 15 ns t ha address hold from write end 0 0 ns t sa address set-up to write start 0 0 ns t pwe we pulse width 13 15 ns t sd data set-up to write end 9 10 ns t hd data hold from write end 0 0 ns t lzwe we high to low z [6] 35ns t hzwe we low to high z [5, 6] 810ns data retention characteristics over the operating range (for l version only) parameter description conditions [10] min. max unit v dr v cc for data retention 2.0 v i ccdr data retention current v cc = v dr = 2.0v, ce > v cc ? 0.3v v in > v cc ? 0.3v or v in < 0.3v 330 a t cdr [3] chip deselect to data retention time 0ns t r [9] operation recovery time t rc ns notes: 9. t r < 3 ns for the -12 and -15 speeds. t r < 5 ns for the -20 ns and slower speeds. 10. no input may exceed v cc + 0.5v.
cy7c1049v33 6 data retention waveform switching waveforms read cycle no. 1 [11, 12] read cycle no. 2 (oe controlled) [12, 13] notes: 11. device is continuously selected. oe , ce = v il . 12. we is high for read cycle. 13. address valid prior to or coincident with ce transition low. 1049v33-5 3.0v 3.0v t cdr v dr > 2v data retention mode t r ce v cc previous data valid data valid t rc t aa t oha 1049v33 ? 6 address data out 1049v33 ? 7 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd high oe ce i cc i sb impedance address data out v cc supply current
cy7c1049v33 7 write cycle no. 1(we controlled, oe high during write) [14, 15] write cycle no. 2 (we controlled, oe low) [15] notes: 14. data i/o is high impedance if oe = v ih . 15. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. 16. during this period the i/os are in the output state and input signals should not be applied. switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe data in valid ce address we data i/o oe note 16 1049v33 ? 8 1049v33-9 data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data i/o note 16 truth table ce oe we i/o 0 ? i/o 7 mode power h x x high z power-down standby (i sb ) l l h data out read active (i cc ) l x l data in write active (i cc ) l h h high z selected, outputs disabled active (i cc )
cy7c1049v33 ? cypress semiconductor corporation, 1999. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. document #: 38 ? 00643 ? b ordering information speed (ns) ordering code package name package type operating range 12 cy7c1049v33-12vc v36 36-lead (400-mil) molded soj commercial cy7c1049v33l-12vc v36 36-lead (400-mil) molded soj 15 cy7c1049v33-15vc v36 36-lead (400-mil) molded soj cy7c1049v33l-15vc v36 36-lead (400-mil) molded soj 17 cy7c1049v33-17vc v36 36-lead (400-mil) molded soj cy7c1049v33l-17vc v36 36-lead (400-mil) molded soj 20 cy7c1049v33-20vc v36 36-lead (400-mil) molded soj cy7c1049v33l-20vc v36 36-lead (400-mil) molded soj cy7c1049v33-20vi v36 36-lead (400-mil) molded soj industrial 25 CY7C1049V33-25VC v36 36-lead (400-mil) molded soj commercial cy7c1049v33-25vi v36 36-lead (400-mil) molded soj industrial package diagram 36-lead (400-mil) molded soj v36 51-85090
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